This invention relates to multiprocessor computer apparatus and more particularly to such apparatus which avoids any processor hierarchy and also avoids employing any centralized switching system.
As discussed in the above-identified patent application, various multiprocessor arrangements have been proposed heretofore. Various specific earlier attempts at a multiprocessor architecture are discussed in greater detail in the previously identified parent application. That discussion is incorporated herein by reference, but certain general considerations are repeated here for background information. As with the present invention, the purpose of such prior art multiprocessor arrangements was to increase computational power and speed by employing a plurality of processor units which would operate in parallel so as to obtain a data through-put greater than that achievable by a single processor operating at any achievable speed. With a few exceptions, most algorithms and computations typically handled by digital computers are susceptible of parallel processing. Further, since the cost of increasing processor speed increases sharply beyond a predetermined point, it can be shown that throughput above a corresponding level can be achieved more economically by employing a greater number of relatively slow processors than by increasing the speed of a single processor. Heretofore, however, these advantages have not been gained without incurring some considerable penalty in terms of system reliability and increases difficulty in programming. These offsetting penalties were typically due to hierarchial organization of the processors. One characteristic often contributing to reliability problems was the usual organizational arrangement where each communications or input-output device was associated with a given one of the processors. Thus, a failure in that one processor might cause the entire system to be unable to fulfill its overall intended purpose.
Among the several objects of the present invention, it may be noted the provision of a multiprocessor computer apparatus providing increased throughput; the provision of such apparatus which is flexible in capacity; the provision of such apparatus which is highly cost-effective; the provison of such apparatus which is highly reliable; the provision of such apparatus which is inherently modular in nature; and the provision of such apparatus which is of relatively simple and inexpensive construction. Other objects and features will be in part apparent and in part pointed out hereinafter.